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Precision Voltage Detector With Programmable Trigger Voltage & Timer Delay
POWER MANAGEMENT Description
The SC1437 is a battery over voltage detection circuit with driver for external MOSFET. The trip point is adjustable with an external resistor divider connected to the SENSE pin. The trip point is preset to a nominal trip voltage of 4.2V if no external divider is used. Other internal trip voltages of 4.5V and 4.7V are available, specified by different part numbers. An internal delay, with two selectable times or bypass, is on-board to suppress accidental over voltage conditions due to glitches on the battery supply voltage, V+. The delay is externally adjustable by pulling the SEL pin high, low, or left floating. During an actual over voltage condition, the internal driver will pull the over voltage pin (OV) down to the voltage present at the V- pin. This insures the external N-Channel MOSFET will be completely off during an over voltage condition. Supply current during the monitoring mode of operation is approximately 10A. If an over voltage condition is detected, supply currents increase when the timer is started. A voltage comparator will engage at voltages greater than 6.8V, which bypasses the timer and open circuits the battery by turning off the external MOSFET. This important function protects the battery during the timer delay in the event of a charger failure. There are three functional options available. With the B option the OV pin is active low. With the L option the OV pin is active high. With the H option the OV pin is open drain, active high. All options are available in a 5 lead SOT-23 package.
SC1437
Features
Low quiescent current, less than 10A typical Input voltage range 1.8V to 6.8V Adjustable or preset voltage trip point Selectable timer delays of 0, 40 and 80ms without use of external resistor ! SOT-23 5 lead package ! Accuracy is 2% over specified temperature range ! 30V maximum rating ! ! ! !
Applications
! ! ! ! ! ! Battery packs Portable electronics Lithium Ion protection circuits Programmable Fuse Power Monitoring CPU Reset Circuits
Typical Application Circuit
+
R1
100 1 SEL SENSE OV V2 V+ 5
100
BATTERY
4 3 R2 0.1uF
SC1437 0.1uF VTRIP = 2.1(1+R2/R1) 0.476 < (R2/R1) < 2
Revision 01/10/2001
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SC1437
POWER MANAGEMENT Absolute Maximum Rating
Par ame te r V+ Sup p ly Voltage to (V-) Over Voltage Outp ut to (V-) Select to (V-) Sense to (V-) Thermal Resistance Junction to Ambient Op erating Ambient Temp erature Range Op erating Junction Temp erature Range Storage Temp erature Range Lead Temp erature (Soldering) 10 sec. ESD Rating (Human Body Model) Symbo l V+ OV SEL SEN SE JA TA TJ TSTG T LE A D ESD Maximum -0.3 to 30 -0.3 to 8 -0.3 to 7 -0.3 to 7 256 -40 to +85 -40 to +125 -65 to +150 300 2 Units V V V V C/W C C C C kV
Electrical Characteristics
Unless specified, TA = 25 OC, V+ = 1.8V to 6.3V. Values in bold apply over the full operating temperature range.
Par ame te r Inp ut Sup p ly Voltage Inp ut Sup p ly Current Over Voltage Threshold with Resp ect to VSymbo l V+ I+ V T R IP Te st Co nditio ns Battery inp ut voltage With internal divider; V+ = 4.7V SEN SE = V-, 4.2V Op tion SEN SE = V-, 4.5V Op tion SEN SE = V-, 4.7V Op tion External Divider, VSENSE + 2.1V, VSENSE = 1V to 4.2V Inp ut Bias Current IBSEN IBSEL OV Threshold Hystersis hyst Sense Pin Select Pin SEN SE = V-, 4.2V Op tion SEN SE = V-, 4.5V Op tion SEN SE = V-, 4.7V Op tion SEN SE = resistor divider OV Drive Current OVDRV B Version H & L Version; R = 100K, V+ = 4.2V Delay tdelay With SEL = V+ With SEL = VWith SEL = no connect Clamp Voltage Turn Off Time Turn-Off Time VCLMP toff toffbpt Step Voltage = 3V to 15V Turn off time of external FET with gate cap = 1nF 6.8V Byp ass Timer Comp arator 50 24 48 420 450 470 VTRIP* 0.1 150 42 0 40 80 6.8 50 56 112 V sec sec uA uA ms 4.12 4.41 4.61 MI N 1 .8 10 4.2 4.5 4.7 2 1 1 T YP MAX 6.3 14 4.28 4.59 4.79 Units V A V V V % A A mV
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SC1437
POWER MANAGEMENT Pin Configuration
Top View
Ordering Information
DEVICE(1) SC1437ISK-BXXTR SC1437ISK-HXXTR PACKAGE SOT-23-5L SOT-23-5L SOT-23-5L
SEL
1
5
V+
SC1437ISK-LXXTR
V-
2
Notes: (1) Where XX = 42 (4.2V), 45 (4.5V), 47 (4.7V) Only available in tape and reel packaging. A reel contains 3,000 devices.
OV
3
4
SENSE
SOT-23-5L
Marking Information
Top Mark Bottom Mark
7B45
7 = SC1437 Device Output Option: B = Output active low L = Output active high H = Output active high, with open drain Voltage Option: 42 = 4.2V; 45 = 4.5V; 47 = 4.7V
yyww
yy = two-digit year of manufacture ww = two-digit week of manufacture
Pin Descriptions
Pin # 1 2 3 4 5 Pin Name SEL VOV SEN SE V+ Pin Function Inp ut for timer delay selection (V+, gnd or no connect). N egative terminal of charger. Over-voltage outp ut. Active low for version B. Active high for versions H & L. Voltage divider inp ut for adjusting over voltage trip p oint. Tie to V- for voltage monitor configuration. Inp ut sup p ly p in.
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SC1437
POWER MANAGEMENT Block Diagram
V+ V+ V+
COMPARATOR
6.8V CLAMP
MUX
4.2V*
V+ V+
DELAY TIMER
SENSE
DRIVER
OV
t
SEL
V-
* Based on version selected 4.2V, 4.5V, 4.7V t B option: Output active low L option: Output active high H option: Output active high, open drain
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SC1437
POWER MANAGEMENT Applications Information
The SC1437 can be used as a battery over voltage detection circuit with driver for an external MOSFET. In this configuration the SC1437 is capable of protecting the battery if the charger circuit fails. Because of its low cost, the SC1437 is an excellent choice in cases when primary discharge protection is not required. The part is an excellent choice for secondary over voltage protection where the battery has primary fault and discharge protection, but could benefit by adding another line of defense against charger failure. The SC1437 comes in three voltage trip options and three function options. The voltage options are 4.2V, 4.5V or 4.7V. In addition, the trip voltage levels can be adjusted with an external resistive divider. The SC1437 also has three separate functional options that affect the OV pin action: With the B option, the OV pin is active low and is used to drive an N-Channel MOSFET. With the H option, the OV pin is active high with open drain to drive a P-Channel MOSFET. Finally, the L option is active high and it's output is 5V logic high for specific use as a voltage detector flag. Any part can be configured as a voltage detector as shown in Figure 1. A programmable trip delay can be set as indicated by Table 1. In Figure 1, the trip voltage is set externally by R1 & R2. while the trip delay is set to 0 seconds plus any propagation delay of the SC1437 to allow the MOSFET to turn off, specified by parameter toff. allows the trip delay to be set to 0S, 40mS or 80mS by application of a jumper JP2, JP3 or leaving the jumper off, respectively. Configuration of timing delays are shown in Table 1. Once the trip delay is set to the required value the SC1437 will monitor the charger voltage. If the charger voltage equals or exceeds 5.5V the OV pin will transition from high to low (Version B) turning Q1 off, thereby breaking the circuit and protecting the battery from overvoltage. Figure 3 shows the trip delay of 80mS, while Figure 4 shows the trip delay set to 40mS and Figure 5 shows no delay set.
FIGURE 1
VSENSE+
R4 100 1 2 VTRIP 3
U1 SEL VOV SENSE SC1437 4 V+ 5
R3 100
R1
C2 0.1uF
C1 0.1uF
R2
VSENSE-
VOLTAGE DETECTOR: TRIP DELAY = 0
VTRIP = 2.1(1+R2/R1) 0.476 < (R2/R1) < 2 When using the program resistors R1 & R2, Figure 2, to set an alternate trip voltage, be sure these resistors are placed across the battery on the drain side of the MOSFET. This will eliminate any voltage drop errors caused by the MOSFET on resistance. Figure 6 and Figure 7 shows the normalized trip voltage variation with respect to temperature. Note that in all cases the trip voltage remains within its 2% specified range. This is true for both the internal trip voltage and externally set trip voltage, however when using an external resistor divider, the tolerance and temperature coefficient of the resistors will add to the overall device error. Choice of the resistor tolerance and temperature coefficient will depend on your error budget. We also recommend using high value resistors to limit battery current drain. Values between 100K and 1M should suffice without introducing excessive noise into the IC.
TABLE 1
SEL CONNECTION V+ VOPEN DELAY N O DELAY 40mS 80mS
CHARGER OVER OLT VERV PRO CHAR GER O VER V OLTA GE PR OTECTION
The SC1437 configuration for secondary overvoltage protection is shown in Figure 2. This is the Evaluation Board schematic. The Evaluation Board is set up to work with either internal trip voltage or external trip voltage via R1 and R2. It also can set the trip delay to all three values through jumper selection of JP2 and JP3. With CHARGER+ and CHARGER- input applied, the charger voltage will be filtered by R3 and C1. The filtered voltage will then be sensed by the V+ input. In this case the trip voltage can be set to a value other than the internal setting of 4.2V. This is done by using the on-board external resistor divider and removing JP1 shunt jumper that will allow the resistors R1 and R2 to program a trip voltage of 5.75V. The Evaluation Board also
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CHOOSING THE EXTERNAL MOSFET
The external switch must be a logic level MOSFET. Most logic level MOSFETs have threshold voltages in the 1V range and can handle a gate to source voltage (VGS) of 12V which is well above the clamp voltage of the SC1437. In addition, the selection should be able to handle the charging current of the battery over all temperature ranges. Whether to use a P-Channel or N-Channel MOSFET depends upon the option chosen. The B option requires the use of a N-Channel MOSFET while the H option uses a P-Channel MOSFET.
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SC1437
POWER MANAGEMENT Applications Information Continued
NO JUMPER = 80ms DELAY
VBAT+ 1 R1 576K JP3 0 DELAY 1 2 JP2 40ms DELAY 1 2 R4 100 1 4 VTRIP 1 3 R3 100 1 CHARGER+
U2 SEL SENSE OV SC1437 C1 0.1uF V+ V5 2
R2 1M
C2 0.1uF
JP1 JUMPER IN = INTERNAL VTRIP SELECT JUMPER OUT = ADJUSTABLE VTRIP SELECT 2 4 VBAT- 1 5 6 7 8 1 2 3 Q1 IRF7805
1
1
CHARGER-
FIGURE 2
Trip Delay set to FIGURE 3: Trip Delay se t to 80mS, JP3 & JP2 Open.
Trip delay Set to Short FIGURE 4: Trip delay Se t to 40mS, JP2 Shor ted.
Top Trace: Charger Voltage, 5V/div Bottom Trace: VTRIP, 5V/div Timebase: 20ms/div
Top Trace: Charger Voltage, 5V/div Bottom Trace: VTRIP, 5V/div Timebase: 20ms/div
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SC1437
POWER MANAGEMENT Applications Information Continued
Trip delay Set to Short FIGURE 5: Trip delay Set t o 0mS, JP3 Shor ted. Internal Trip Voltage Deviation FIGURE 6: Int ernal Trip Voltage (4.7V) De viation Plott tted Against Tem emperature. Plo tt ed A gainst Tem perature.
INTERNAL TRIP VOLTAGE DEVIATION OVER TEMPERATURE
0.4 0.2 DEVIATION (%) 0 -0.2 -0.4 -0.6 -0.8 -1 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (Degrees C) 4.7V Internal
Top Trace: Charger Voltage, 5V/div Bottom Trace: VTRIP, 5V/div Timebase: 20ms/div FIGURE 7: Int ernal Trip Voltage (4.2V) Deviation 7: Internal Trip Voltage Deviation Plott tted Against Tem emperature. Plo tt ed A gainst Tem perature.
INTERNAL TRIP VOLTAGE DEVIATION OVER TEMPERATURE
0.2 0.1 DEVIATION (%) 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (Degrees C) 4.2V Internal
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SC1437
POWER MANAGEMENT Outline Drawing - SOT23-5
Land Pattern - SOT23-5
Contact Information
Semtech Corporation Power Management Products Division 652 Mitchell Rd., Newbury Park, CA 91320 Phone: (805)498-2111 FAX (805)498-3804
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